1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which is provided with an A/D converter, more particularly, to a semiconductor integrated circuit which is provided with a circuit capable of applying multiplication and complement operation to the A/D converter.
2. Description of the Prior Art
A digital signal process is intended for high performance, high integration and high function as a digital integrated circuit technique has been recently proceeded even in a field of a conventional signal process by an analog circuit. A/D converters are indispensable to digitally process an originally analog signal, such as a voice or an image.
FIG. 1 shows a conventional parallel comparison type A/D converter. Referring to FIG. 1, the A/D converter includes a reference voltage terminal 21, an analog input terminal 22, ladder resistors 23 connected in series between the reference voltage terminal 1 and a ground for determining the reference voltages of comparators 24, a plurality of comparators 24 aligned in parallel with each other, an encoder circuit 25, and digital output terminals 26 connected to the outputs of the encoder 25.
With such arrangement of the conventional A/D converter, a voltage applied to the reference voltage terminal 21 is divided by the plurality of ladder resistors 23 connected in series, and reference voltage thus divided from the voltage by the respective ladder resistors 23 are sequentially applied to one inputs of the plurality of comparators 24, respectively. The comparators 24 compares the inputs of the reference voltages with the analog signal inputted to the analog input terminal 22, and outputs the compared results. The output of the comparators 24 are coded by the encoder circuit 25, and digital data are outputted to the output terminals 26 connected to the outputs of the encoder circuit 25. When the output includes N bits, the number of the comparators requires (2.sup.N -1) pieces.
The conventional A/D converter will be described in more detail by referring to FIGS. 2 and 3. FIG. 2 shows a parallel comparison type A/D converter of 3-bit straight binary code output, and FIGS. 3(a) and 3(b) show examples of the outputs of the comparators and the outputs of the encoder circuit of the A/D converter. This A/D converter is of parallel-comparison format, and thus, all the signals outputted from comparators are either "1" (high) or "0" (low), or the upper bit row becomes "0" and the lower bit row "1", respectively. Of these, the unit number of bit "1" denotes the analog input value in the decimal notation. The A/D converter of FIG. 2, the values of the outputs are difference between 24b and 24c.
When the encoder 25 is constructed as shown in FIG. 2 in the conventional A/D converter with the comparators 24 connected to the inputs of the encoder 25 as shown in FIG. 3(a), the output of the encoder 25 (the bit 26a is the most significant bit) produces "5" as shown in FIG. 3(b) with respect to the comparison output "5".
Since the conventional A/D converter is constructed as described above, a multiplier of another chip is required for producing a product of the digital output of the A/D converter and other data. Further, when a high speed multiplier is constructed, there arise drawbacks that the chip area of the multiplier of another chip is increased, and a number of multipliers must be integrated on the same chip.
To fully solve those problems mentioned above, inventors developed a semiconductor integrated circuit capable of mounting a circuit having functions of A/D converter and multiplier on a single chip. This prior invention was filed for the application for a U.S. Patent under the USP Application No. S.N. 07/111,047. The above-cited semiconductor integrated circuit is comprised of the following; a plurality of comparators for comparing the analog input signal with the reference voltage denoting the divided value of the power voltage, and multiplication means which controls signals outputted from those plural comparators mentioned above by applying control signals based on the inputted digital value and then outputs the result of the multiplication of the signal values outputted from those plural comparators by the input digital value. FIG. 4 denotes the semiconductor integrated circuit provided with those comparators and multiplication means mentioned above. The semiconductor integrated circuit shown in FIG. 4 receives 2-bit digital value for example. The semiconductor integrated circuit shown in FIG. 4 is provided with the following; ladder resistor 1 which divides the power voltage into reference voltages for each comparator; a plurality of comparators 2a, 2b ... for comparing the reference voltage to the inputted analog value; multiplication means 3 which encodes the inputted analog value into binary digital code and then output the product of the binary digital code and the inputted digital value; digital value input terminals 6a and 6b; product output terminals 9a through 9d; overflow bit terminal 8 which outputs binary digital code "1" when the inputted analog value is greater than each reference voltage; analog input terminal 10; and power voltage terminal 11, respectively.
Next, functional operation of the semiconductor integrated circuit related to the prior invention is described below. First, when the power voltage is delivered to the power-voltage terminal 11, ladder resistor 1,1 ... respectively divide the power voltage into reference voltages. Next, when the inputted analog value is delivered to analog input terminal 10, those reference voltages and the voltage of the inputted analog value are then delivered to comparator 2a, 2b ... . The comparator 2a, 2b ... compares the magnitude of the two inputted voltages, which outputs binary digital code "1" if the voltage of the inputted analog value is higher than those reference voltages. For example, each signal outputted from comparators 2a, 2b ... corresponds to value 2 of the decimal notation of the inputted analog value in case as shown in FIG. 5(a). Next, when the digital-value input terminals 6a and 6b respectively receive binary-encoded data denoting "3" of the decimal notation as shown in FIG. 5(b), the product output terminals 9a through 9d respectively output data as shown in FIG. 5(c) denoting the result of the multiplication (inputted analog value 2).times.(inputted digital value 3) =(product output value 6).
Nevertheless, since the semiconductor integrated circuit related to the prior invention is not provided with any terminal for receiving sign bits, this integrated circuit merely deals with the positive inputted digital values, and thus, if any negative inputted digital value is received, this integrated circuit cannot output the product of multiplication at all.